1. Field
The innovations herein relate to static random access memory, and, more particularly, to systems and methods relating to SRAMs involving sectioned bit lines in memory arrays, including embodiments arranged in hierarchical manner.
2. Description of Related Information
In high density static memory arrays, considerable effort is directed towards minimizing bit line capacitance. Bit line capacitance affects the speed of memory cell sensing and overall stability of memory cells. One way to reduce bit line capacitance is to reduce memory cell size, which is sometimes feasible though is subject to technological limitations. By reducing the memory cell size, the bit line is shortened but the memory cell active current is also reduced. Consequently, the overall performance of memory array may generally stay about the same. Performance may also be improved by reducing the number of memory cells on any given bit line. However, known practices in conventional SRAMs that maintain sensing speed typically entail reducing memory arrays density, which yields larger array area(s). Overall, such existing systems and methods suffer drawbacks relating to the failure to achieve smaller bit line capacitance in desired higher density memory arrays.
Other known systems and methods, such as with some DRAMs and folded bit line structures used in conventional DRAM, may include local bit line connected to gates of access transistors that pass representations of the local bit line onto a global bit line. However, such existing systems and methods may have one or more of a variety of drawback, such as being limited to having very small quantities of memory cells per bit line and thus very short bit lines due to their reduced sensing capability. Voltage swings associated with the bit lines of such systems and methods also tend to be large because of threshold voltage of gate. Further, such systems also suffer drawbacks related to the pass gates being gate-connected the local bit line, to passing an inverse of the signal on the local bit line, and/or to being pre-charged to high instead of low.
Moreover, DRAM implementations and folded bit line structures used in the conventional DRAM relate to a variety of disparate structural or operational issues and/or restrictions. For one, bit lines are typically charged to half Vcc in DRAM. Further, for example, folded bit line structures associated with conventional DRAMs are limited to two pairs of bit lines arranged on either side of the relevant sense amplifier. Also, due to the destructive nature of DRAM cell reading, various DRAM cells need to be sensed once a memory cell is turned on. Accordingly, there can only be one DRAM cell selected for every sense amplifier. Hence, as there can only be one memory cell selected on either the true bit line or the complement bit line, disparate issues associated with selecting memory cells on both at the same time are not present. Moreover, with DRAM, the word lines are not shared by the memory cells on the true bit line and complement bit line. In a hierarchical bit line DRAM, for example, when one memory cell is selected on the true local bit line, there can be no memory cell selected on the complement local bit line at the same time. And no issues related to selection of pass gates coupling the complement local bit lines and the complement global bit lines are present, either. The complement global bit line, e.g., is simply used as a sensing reference in some cases. As such, among the other issues noted above, no design considerations relating to selecting more than only the pass gate on the true local bit line are encountered/overcome.
In sum, as detailed in the innovations below, there is a need for the present systems and methods that may achieve smaller bit line capacitance, improved memory cell stability and/or higher density memory arrays.